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AI-Based Chip Design: 1000X Performance Boosts Within Ten Years
Chip design is undergoing a revolution in capabilities as AI is being integrated into the design process. Chip design automation tools were first introduced in the 1980’s with the introduction of computer-based layout applications. Now, in the 2020’s, AI tools are being added by chip design companies like Synopsis and Cadence Design and the Aart de Geus, CEO at Synopsis, predicts that as these tools improve over the next decade, will lead to a factor of 1000x improved chip design quality and development times. This may be the missing piece that will allow Moore’s law to continue.
de Geus said that “in many ways, I consider that we cracked the code on opening a whole new phase of how design is occurring. 35 years ago we cracked the code and it changed design – the similarities are uncanny.”
What’s different this time around is that previous innovations where task-centric with improvements in a suite of tools for the whole process. This time around, AI chip design is changing the entire flow, from start to end. AI is able to include consideration of an enormous number of multi-dimensional parameters, something that a human just can not do.
de Geus said that “helping the human designer move up to be more of an architect is not any different than it was 35 years ago. It’s about having the designer move up to deal with bigger problems because certain pieces are being solved in a way that’s even better than they could do, even if they had infinite time”
He said that “I think we have had the end of classic Moore’s Law. And I believe this new era is moving from scale complexity to systemic complexity. I think the ambition is very high.”
Karl Freund of Cambrian AI Research, said that “it is important to point out that these AI platforms do not just output an answer to “do this”. The design team is presented with alternatives that can optimize performance, power, cost, or more likely a combination of all three. In one example, the team could choose to increase performance by 15%, or reduce size (and cost) by 18%. Or the team could blend the two designs and increase performance by 8% while still reducing die size.”
