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Open Source Chip Design: Lowering the Cost, but Chip Production Remains Expensive

By Dick Weisinger

The recent history of computer chips has seen the market dominated by very large market players that have invested large amounts of cash to produce ultra-miniature and highly complex semiconductors.

Those industry players aren’t expected to change much in the near term, but the market and model for creating and using chips is changing. Increasingly it is possible for non-elite chip manufacturing companies to develop customized chips for specialized applications

Mike Dolan, the Linux Foundation’s vice president, said that “open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards. The same collaboration model applies to the hardware in a system, just as it does to software components.”

RISC-V is an Open Source project for CPU design. The architecture was originally developed at UC Berkeley and ultimately turned over to the public domain as an Open Source design. It offers a clean architecture and a low-cost point for entry into CPU design.

As businesses look for ways to differentiate themselves and to create applications with hardware tuned specifically to their use case, open source may provide them an alternative to mass-produced generic semiconductor chips.

But, while there are similarities, hardware and software have distinct differences and costs. Aaron Sullivan, engineer at Meta/Facebook, said that “with open-source software we have compilers and fairly good management tools for source code. For open-source hardware, we also need fabs. They are expensive and not nearly as plentiful or distributable. They require a lot of expertise to run and develop. That is a critical difference in the rate in which the community can mature.”

Bipul Talukdar, Director of Applications Engineering at SmartDV, wrote that “chip design verification is important to remove risk by uncovering issues that would result in a manufactured chip that does not perform to specification or perhaps not even work at all. Verification consumes a majority of the project development schedule. Estimates range from 60% to 80% of a project’s resources are budgeted for verification to ensure success. The risk of a failed design can be expensive when considering longer time to market, resource costs and costs associated with respins. A respin on a complex chip being manufactured in an advanced process technology can be more expensive than the investment in tools and IP used to create the chip design itself.”

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